1. Field
The present disclosure relates to an organic light emitting diode display device capable of cutting off a leakage current.
2. Related Art
Recently, development of various types of flat panel displays (FPDs) is being accelerated. Among others, organic light emitting diode display devices use self-light emitting elements, providing large advantages of fast response time, high light emitting efficiency and brightness, and a large field of view.
An organic light emitting diode display device incorporates organic light emitting diodes as shown in FIG. 1. An organic light emitting diode comprises an organic compound layer. The organic compound layers consists of a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). If a driving voltage is applied to the anode and the cathode, holes which have passed the hole transport layer (HTL) and electrons which have passed the electron transport layer (ETL) move to the emission layer (EML) and form excitons; and as a result, the emission layer (EML) generates visible light.
An organic light emitting diode display device arranges pixels including organic light emitting diodes as described above in the form of a matrix and controls brightness of the pixels according to the gray scale of video data.
Organic light emitting diode display devices are getting great attention as display devices for mobile applications. An organic light emitting diode display device employed for mobile applications comprises a power supply unit 1, a display unit 2, and a driving unit 3 as shown in FIG. 2.
The power supply unit 1 is equipped with a power IC P-IC. The power IC P-IC receives a battery power VBAT through an input terminal Vin and by using the battery power VBAT, generates an OLED driving voltage VDD_OLED applied to the display unit 2.
The display unit 2 comprises a plurality of pixels, each of which consisting of 6T1C (i.e., six TFTs and one capacitor). Individual pixels are built to have such a structure that prior to a programming stage, a gate node N1 of a driving TFT DT is initialized by a reference voltage VREF applied from the driving unit 3 at the initialization stage.
The driving unit 3 provides pixel data to data lines of the display unit 2, scan signals SCANs to the gate lines of the display unit 2, and emission signals EMs to the emission lines of the display unit 2. The driving unit 3 activates the power IC P-IC by applying an enable signal EN to the power supply unit 1 at a display mode while deactivating the power IC P-IC by applying a disable signal DIS to the power supply unit 1 at a sleep mode. The sleep mode is intended for reducing power consumption of mobile applications, indicating an operation mode where display is temporarily turned off when no input is received from the user for a predetermined time period. The driving unit 3 is in normal operation at the sleep mode. The driving unit 3 generates the reference voltage VREF and applies the reference voltage to the display unit 2. The driving unit 3 is equipped with an output buffer to generate the reference voltage VREF. The output buffer comprises a first PMOS switch PMT1 and a first NMOS switch NMT1 connected in series between a power voltage Vs and the ground. The gate block of the first PMOS switch PMT1 and the first NMOS switch NMT1 are all in a floating state (i.e., Hi-Z stage).
A true shutdown function is excluded from the power IC P-IC for the purpose of reducing power consumption and increasing efficiency. The true shutdown function denotes automatically cutting off the battery power VBAT applied to the input terminal Vin of the power IC P-IC inside the power IC P-IC when the disable signal DIS is applied from the driving unit 3 or a system (not shown). The power IC P-IC excluding the true shutdown function is unable to cut off the leakage current due to the battery voltage VBAT from being applied to the display unit 2 in a disable state. In this regard, the organic light emitting diode display device further comprises a second NMOS switch NMT2 between and the ground and the cathode of an organic light emitting diode (OLED) formed in the display unit 2. As the second NMOS switch NMT2 is turned off according to a current path control signal CTS from the driving unit 3, a current path between an input load of the power IC P-IC and the display unit 2 is blocked and thus, generation of a leakage current is prevented.
On the other hand, during the initialization stage, since TFTs of pixels are all turned on according to the scan signal SCAN and the emission signal EM, a leakage current may develop along the path shown in FIG. 2 for an organic light emitting diode display device initializing a gate node N1 of the driving TFT (DT) through the reference voltage VREF generated at the driving unit 3, even if the second NMOS switch NMT2 is staying in a turn-off state. The amount of the leakage current increases in proportion to a potential difference between the input terminal of an OLED driving voltage VDD_OLED and the reference voltage VREF output terminal of the driving unit 3.